lcd16x2_ctrl_demo Project Status
Project File: VHDL_LCD_tutorial.xise Parser Errors: No Errors
Module Name: lcd16x2_ctrl_demo Implementation State: New
Target Device: xc6slx9-3csg324
  • Errors:
 
Product Version:ISE 14.7
  • Warnings:
 
Design Goal: Balanced
  • Routing Results:
 
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
 
Environment: System Settings
  • Final Timing Score:
  
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis Report     
Translation Report     
Map Report     
Place and Route Report     
Power Report     
Post-PAR Static Timing Report     
Bitgen Report     
 
Secondary Reports [-]
Report NameStatusGenerated
WebTalk ReportCurrentThu Jan 21 23:10:18 2016
WebTalk Log FileCurrentThu Jan 21 23:10:27 2016

Date Generated: 01/24/2016 - 19:19:31