lcd16x2_ctrl_demo Project Status
Project File: VHDL_LCD_tutorial.xise Parser Errors: No Errors
Module Name: lcd16x2_ctrl_demo Implementation State: Programming File Generated
Target Device: xc6slx9-3csg324
  • Errors:
No Errors
Product Version:ISE 14.7
  • Warnings:
No Warnings
Design Goal: Balanced
  • Routing Results:
All Signals Completely Routed
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
All Constraints Met
Environment: System Settings
  • Final Timing Score:
0  (Timing Report)
 
Device Utilization Summary [-]
Slice Logic UtilizationUsedAvailableUtilizationNote(s)
Number of Slice Registers 72 11,440 1%  
    Number used as Flip Flops 72      
    Number used as Latches 0      
    Number used as Latch-thrus 0      
    Number used as AND/OR logics 0      
Number of Slice LUTs 198 5,720 3%  
    Number used as logic 198 5,720 3%  
        Number using O6 output only 129      
        Number using O5 output only 2      
        Number using O5 and O6 67      
        Number used as ROM 0      
    Number used as Memory 0 1,440 0%  
Number of occupied Slices 68 1,430 4%  
Number of MUXCYs used 52 2,860 1%  
Number of LUT Flip Flop pairs used 203      
    Number with an unused Flip Flop 131 203 64%  
    Number with an unused LUT 5 203 2%  
    Number of fully used LUT-FF pairs 67 203 33%  
    Number of unique control sets 4      
    Number of slice register sites lost
        to control set restrictions
16 11,440 1%  
Number of bonded IOBs 8 200 4%  
    Number of LOCed IOBs 8 8 100%  
Number of RAMB16BWERs 0 32 0%  
Number of RAMB8BWERs 0 64 0%  
Number of BUFIO2/BUFIO2_2CLKs 0 32 0%  
Number of BUFIO2FB/BUFIO2FB_2CLKs 0 32 0%  
Number of BUFG/BUFGMUXs 1 16 6%  
    Number used as BUFGs 1      
    Number used as BUFGMUX 0      
Number of DCM/DCM_CLKGENs 0 4 0%  
Number of ILOGIC2/ISERDES2s 0 200 0%  
Number of IODELAY2/IODRP2/IODRP2_MCBs 0 200 0%  
Number of OLOGIC2/OSERDES2s 0 200 0%  
Number of BSCANs 0 4 0%  
Number of BUFHs 0 128 0%  
Number of BUFPLLs 0 8 0%  
Number of BUFPLL_MCBs 0 4 0%  
Number of DSP48A1s 0 16 0%  
Number of ICAPs 0 1 0%  
Number of MCBs 0 2 0%  
Number of PCILOGICSEs 0 2 0%  
Number of PLL_ADVs 0 2 0%  
Number of PMVs 0 1 0%  
Number of STARTUPs 0 1 0%  
Number of SUSPEND_SYNCs 0 1 0%  
Average Fanout of Non-Clock Nets 3.58      
 
Performance Summary [-]
Final Timing Score: 0 (Setup: 0, Hold: 0, Component Switching Limit: 0) Pinout Data: Pinout Report
Routing Results: All Signals Completely Routed Clock Data: Clock Report
Timing Constraints: All Constraints Met    
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentTue Jan 19 22:28:18 2016001 Info (1 new, 0 filtered)
Translation ReportCurrentTue Jan 19 22:28:39 2016001 Info (0 new, 0 filtered)
Map ReportCurrentTue Jan 19 22:29:31 2016006 Infos (6 new, 0 filtered)
Place and Route ReportCurrentTue Jan 19 22:30:18 2016000
Power Report     
Post-PAR Static Timing ReportCurrentTue Jan 19 22:30:44 2016003 Infos (3 new, 0 filtered)
Bitgen ReportCurrentTue Jan 19 22:37:46 2016000
 
Secondary Reports [-]
Report NameStatusGenerated
WebTalk ReportCurrentTue Jan 19 22:37:52 2016
WebTalk Log FileCurrentTue Jan 19 22:38:00 2016

Date Generated: 01/21/2016 - 21:19:36