galatea_not_gate Project Status (08/29/2017 - 14:39:16)
Project File: notgate.xise Parser Errors: No Errors
Module Name: galatea_not_gate Implementation State: Placed and Routed (Failed)
Target Device: xc6slx45t-3fgg484
  • Errors:
No Errors
Product Version:ISE 14.7
  • Warnings:
No Warnings
Design Goal: Balanced
  • Routing Results:
All Signals Completely Routed
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
 
Environment: System Settings
  • Final Timing Score:
0  
 
Device Utilization Summary [-]
Slice Logic UtilizationUsedAvailableUtilizationNote(s)
Number of Slice Registers 0 54,576 0%  
Number of Slice LUTs 0 27,288 0%  
Number of occupied Slices 0 6,822 0%  
Number of MUXCYs used 0 13,644 0%  
Number of LUT Flip Flop pairs used 0      
Number of bonded IOBs 2 296 1%  
Number of RAMB16BWERs 0 116 0%  
Number of RAMB8BWERs 0 232 0%  
Number of BUFIO2/BUFIO2_2CLKs 0 32 0%  
Number of BUFIO2FB/BUFIO2FB_2CLKs 0 32 0%  
Number of BUFG/BUFGMUXs 0 16 0%  
Number of DCM/DCM_CLKGENs 0 8 0%  
Number of ILOGIC2/ISERDES2s 0 376 0%  
Number of IODELAY2/IODRP2/IODRP2_MCBs 0 376 0%  
Number of OLOGIC2/OSERDES2s 0 376 0%  
Number of BSCANs 0 4 0%  
Number of BUFHs 0 256 0%  
Number of BUFPLLs 0 8 0%  
Number of BUFPLL_MCBs 0 4 0%  
Number of DSP48A1s 0 58 0%  
Number of GTPA1_DUALs 0 2 0%  
Number of ICAPs 0 1 0%  
Number of MCBs 0 2 0%  
Number of PCIE_A1s 0 1 0%  
Number of PCILOGICSEs 0 2 0%  
Number of PLL_ADVs 0 4 0%  
Number of PMVs 0 1 0%  
Number of STARTUPs 0 1 0%  
Number of SUSPEND_SYNCs 0 1 0%  
Average Fanout of Non-Clock Nets 1.00      
 
Performance Summary [-]
Final Timing Score: 0 (Setup: 0, Hold: 0) Pinout Data: Pinout Report
Routing Results: All Signals Completely Routed Clock Data: Clock Report
Timing Constraints:      
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentTue 29. Aug 14:37:53 2017000
Translation ReportCurrentTue 29. Aug 14:37:58 2017000
Map ReportCurrentTue 29. Aug 14:38:07 2017006 Infos (6 new)
Place and Route ReportCurrentTue 29. Aug 14:38:16 2017002 Infos (2 new)
Power Report     
Post-PAR Static Timing Report     
Bitgen Report     
 
Secondary Reports [-]
Report NameStatusGenerated

Date Generated: 08/29/2017 - 14:39:16