Hi, I have some more time now and want to get this working. Looking over the VHDL I have two questions: 1. I tried disabling the multiplier and the barrel shifter to see how much area could be saved. This reduced the utilization from 57% to 50% of slices. Is this recommended or discouraged? 2. As I understand it the BRAM is generated from slices in the FPGA but can I use the BRAM generator in ISE to instead use the dedicated BRAM resources to reduce utilization?