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Elbert V2 Clock Speed

Discussion in 'FPGA Boards' started by Tom Maynard, Nov 8, 2015.

  1. Tom Maynard

    Tom Maynard New Member

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    The User's Guide makes no mention of the clock speed for the Elbert V2. The UCF file clearly states, " # Clock 12 MHz" but my empirical observations seem to belie that speed.

    Example Verilog code to generate a 440 Hz tone at the audio port:

    module A440(
    input Clk,
    output AUDIO_L,
    output AUDIO_R
    );

    reg[15:0] counter;
    always @(posedge Clk) if (counter == 27273) counter <= 0; else counter <= counter + 1;

    assign AUDIO_L = counter[15];
    assign AUDIO_R = counter[15];
    endmodule
    Produces an inaudible frequency (12e6 / 440 = 27.273e3). Using a value like 56.818e3 does produce an audible tone, but at what frequency? (I'm unconcerned about the duty cycle at this point.)

    What is the actual frequency of Elbert's clock?
     
  2. Alexander Lang

    Alexander Lang Member

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    Hi Tom,

    The frequency of the input clock on an Elbert V2 board is 12 MHz. If you look at the board the crystal oscillator is clearly visible. I have attached a picture showing the crystal on the PCB.

    I unfortunately am not great at coding with verilog so I cannot be sure of how your code functions although I will take a look and try it! It doesn't look overly complex. Have you simulated the output with a test bench to check that results are as expected.

    If things are not working as expected then normally in my experience with my own code it's normally a mistake somewhere.

    I will take a look for you and hopefully between the pair of us we can get something working. Could you attach your code and UCF file so I can refer to it.

    Cheers

    Alex
     

    Attached Files:

  3. Alexander Lang

    Alexander Lang Member

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    I looked into this and I tested your code and you are quite correct. When you use an integer value of 27273 which should equate to 440 Hz nothing audible is heard. I then replaced that value with 56818 and I could here a tone which I matched with my piano to just off 'A'....- Piano must need tuning! I will when I have time measure the frequency using an oscilloscope to check it. This suggests that the clock frequency was 25 MHz and not 12 MHz which doesn't make sense. I suspect there is something I'm not accounting for here....

    I take it you are using the examples on FPGA4fun.com to learn VHDL - great site!
     

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