I am trying to setup the sample for the IP4776CZ38 HDMI Transmitter with a Mimas v2. I changed the project to target XC6SLX9 and removed the waxwingdevboard.ucf and added the mimasv2.ucf as specified in the readme. The project builds but with many warnings. When flashed it doesn't work (the final warning seems to be most suspect). Here are all the warnings that I get: Code: WARNING:HDLCompiler:1127 - "D:\xxx\Downloads\fpga\mimas\samplecode-master\FPGA\ExpansionModules\IP4776CZ38HDMITransmitter\src\spartan6\Clocking.v" Line 126: Assignment to locked_int ignored, since the identifier is never used WARNING:HDLCompiler:1127 - "D:\xxx\Downloads\fpga\mimas\samplecode-master\FPGA\ExpansionModules\IP4776CZ38HDMITransmitter\src\spartan6\Clocking.v" Line 127: Assignment to status_int ignored, since the identifier is never used WARNING:HDLCompiler:1127 - "D:\xxx\Downloads\fpga\mimas\samplecode-master\FPGA\ExpansionModules\IP4776CZ38HDMITransmitter\src\spartan6\IP4776CZ38ExpansionModuleTransmitter.v" Line 56: Assignment to bufpll_lock ignored, since the identifier is never used WARNING:Xst:1710 - FF/Latch <c1_q> (without init value) has a constant value of 0 in block <encg>. This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1710 - FF/Latch <c0_q> (without init value) has a constant value of 0 in block <encg>. This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1710 - FF/Latch <c1_q> (without init value) has a constant value of 0 in block <encr>. This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1710 - FF/Latch <c0_q> (without init value) has a constant value of 0 in block <encr>. This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <c0_reg> (without init value) has a constant value of 0 in block <encg>. This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <c1_reg> (without init value) has a constant value of 0 in block <encg>. This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <c0_reg> (without init value) has a constant value of 0 in block <encr>. This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <c1_reg> (without init value) has a constant value of 0 in block <encr>. This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1898 - Due to constant pushing, FF/Latch <n1q_m_0> is unconnected in block <encode>. WARNING:Xst:1710 - FF/Latch <cnt_0> (without init value) has a constant value of 0 in block <encode>. This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1710 - FF/Latch <dvi_encoder/encr/c1_q> (without init value) has a constant value of 0 in block <IP4776CZ38ExpansionModuleTransmitter>. This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1710 - FF/Latch <dvi_encoder/encr/c0_q> (without init value) has a constant value of 0 in block <IP4776CZ38ExpansionModuleTransmitter>. This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1710 - FF/Latch <dvi_encoder/encg/c1_q> (without init value) has a constant value of 0 in block <IP4776CZ38ExpansionModuleTransmitter>. This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1710 - FF/Latch <dvi_encoder/encg/c0_q> (without init value) has a constant value of 0 in block <IP4776CZ38ExpansionModuleTransmitter>. This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dvi_encoder/encr/c1_reg> (without init value) has a constant value of 0 in block <IP4776CZ38ExpansionModuleTransmitter>. This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dvi_encoder/encr/c0_reg> (without init value) has a constant value of 0 in block <IP4776CZ38ExpansionModuleTransmitter>. This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dvi_encoder/encg/c1_reg> (without init value) has a constant value of 0 in block <IP4776CZ38ExpansionModuleTransmitter>. This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dvi_encoder/encg/c0_reg> (without init value) has a constant value of 0 in block <IP4776CZ38ExpansionModuleTransmitter>. This FF/Latch will be trimmed during the optimization process. WARNING:Pack:2768 - At least one timing constraint is impossible to meet because component switching limit violations have been detected for a constrained component. A timing constraint summary below shows the failing constraints (preceded with an Asterisk (*)). Please use the Timing Analyzer (GUI) or TRCE (command line) with the Mapped NCD and PCF files to evaluate the component switching limit violations in more detail. Evaluate the datasheet for alternative configurations for the component that could allow the frequencies requested in the constraint. Otherwise, the timing constraint covering this component might need to be modified to satisfy the component switching limits specified in the datasheet. WARNING:Par:450 - At least one timing constraint is impossible to meet because component switching limit violations have been detected for a constrained component. A timing constraint summary below shows the failing constraints (preceded with an Asterisk (*)). Please use the Timing Analyzer (GUI) or TRCE (command line) with the Mapped NCD and PCF files to evaluate the component switching limit violations in more detail. Evaluate the datasheet for alternative configurations for the component that could allow the frequencies requested in the constraint. Otherwise, the timing constraint covering this component might need to be modified to satisfy the component switching limits specified in the datasheet. WARNING:Par:468 - Your design did not meet timing. The following are some suggestions to assist you to meet timing in your design. If anyone knows if I missed anything please let me know. I'm new to fpga's and just wanted to test this module quick to make sure it works. The mimas works fine with other things I've tested. edit: I'm using ISE 14.7
Hi jneta, Xilinx Spartan 6 devices technically don't support Full HD (1920x1080@60Hz) resolution. That's why timing constraint failed here. But most the monitors are quite tolerant to slight timing deviations, but some might not be. So, if its not working with current resolution, better we should lower it to something like 720p. Please check this link for more on this issue: http://hamsterworks.co.nz/mediawiki/index.php/Spartan_6_1080p Thanks!
