1. This site uses cookies. By continuing to use this site, you are agreeing to our use of cookies. Learn More.

Problem with DAC expansion module

Discussion in 'Expansion Modules & Breakout Bords' started by Sandip Das, Jun 6, 2016.

  1. Sandip Das

    Sandip Das New Member

    Joined:
    Jun 6, 2016
    Messages:
    1
    Likes Received:
    0
    Trophy Points:
    1
    Gender:
    Male
    Location:
    india
    I am trying to get a ramp signal (4 bit) output. I am providing a sequence of 0001, 0010, 0100 and 1000 in a loop to the DB0P1 to DB3P1 port of AD9763 module from MIMUS-V2. I have also provided the CLK1/CLK2, WRT1/WRT2 through proper GPIO pins.
    I have configured the AD9763 module to dual port mode and independent gain control mode. However, I am not getting any signal output at the analog SMA output port of the module.

    The UCF file is posted below for further information. I have connected the module to P6, P7 and P8 header of MIMUs V2.

    NET ramp_axiw_0_clk1_pin LOC = "T8" | DRIVE = "8" | IOSTANDARD = "LVCMOS33";
    NET ramp_axiw_0_clk2_pin LOC = "R5" | DRIVE = "8" | IOSTANDARD = "LVCMOS33";
    NET ramp_axiw_0_wrt1_pin LOC = "R8" | DRIVE = "8" | IOSTANDARD = "LVCMOS33";
    NET ramp_axiw_0_wrt2_pin LOC = "T5" | DRIVE = "8" | IOSTANDARD = "LVCMOS33";
    NET ramp_axiw_0_d_pin[0] LOC = "U8" | DRIVE = "8" | IOSTANDARD = "LVCMOS33";
    NET ramp_axiw_0_d_pin[1] LOC = "V8" | DRIVE = "8" | IOSTANDARD = "LVCMOS33";
    NET ramp_axiw_0_d_pin[2] LOC = "V11" | DRIVE = "8" | IOSTANDARD = "LVCMOS33";
    NET ramp_axiw_0_d_pin[3] LOC = "U11" | DRIVE = "8" | IOSTANDARD = "LVCMOS33";

    The pictures of the setup and the outputs in DSO is posted here.

    I don't understand what's going wrong. Any help is appreciated. If there is any demo application made using this module please share the same.
     

    Attached Files:

Share This Page