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Interface MimasV2 with DDR ram

Discussion in 'FPGA Boards' started by Yatin Deshpande, Aug 16, 2017.

  1. Yatin Deshpande

    Yatin Deshpande New Member

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    I am new on FPGA enviornment and bought MIMAS v2 as it has fast ram and in a impressive cost.
    What my problem is I was trying and searching on internet but i didnt got any example of how to write on DDR ram of Mimas v2 using xilinx or verilog and how to read the same.
    Can any one could guide me on this one?
     
  2. analog_digital

    analog_digital New Member

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    hi,

    Numato provides a "LEARNING FPGA AND VERILOG A BEGINNER'S GUIDE PART 6 - DDR SDRAM" here. It's "getting started" with mimas V2 LPDDR. The board uses standard Xilinx MCB (Memory controller) documented here, a very powerful interface, with our hardware we can get up to 4.256 Gbps of peak bandwidth.

    I'm new to FPGA world and in these days I'm just playing around with this interface :)

    AD

    EDIT: reviewing frequencies, theoric peak bandwith should be 5.312 Gbps
     
    Last edited: Aug 20, 2017
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  3. rohith

    rohith Moderator Staff Member

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  4. Yatin Deshpande

    Yatin Deshpande New Member

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    @analog_digital :- THanks for yous suggestions.
    I was able to interface and blink those calibration done LED.
    But what about That Xilinx EDK it is giving me license key errors!
    So now do i Have ti buy this license or can I do it in free too?
     
  5. analog_digital

    analog_digital New Member

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    Sorry, I'm not an expert about licences, because mine is provided by the University :(. BTW, as far as I know, the free ISE WebPACK should not have any limitation on IP core generator.... take a look here

    AD
     
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  6. rohith

    rohith Moderator Staff Member

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    @Yatin Deshpande Yeah, EDK requires a separate license. You can either buy a licence or get a 30-day trial license.

    Thanks!
     
  7. Yatin Deshpande

    Yatin Deshpande New Member

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    So is there any separate option in which i can do it without this EDK?
    Is there any other software or any other way around or can we do it without core generation?
     
  8. rohith

    rohith Moderator Staff Member

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    @Yatin Deshpande Please take a look at the MCB user guide [UG388] which analog_digital has linked above. The User Guide explains how a generic RTL code can interface with the MCB controller. I've also posted links from hamsterworks which provide an example of how to use the MCB IP core in with VHDL code.
     

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