Hi, IS there any working example project for the Mimas (v1) and the CS4344 audio expansion module? I tried the examples in Numato svn here -> http://svn.numato.cc/svn/numatocc/FPGA/SampleCode/ExpansionModules/ and almost all of them can be compiled successfully for my board (MimasV1) when I select the proper chip and board .ucf, though the CS4344 example cannot compile successfully giving errors ERRORlace:1205 - This design contains a global buffer instance, <c1/CLKFX_BUFG_INST>, driving the net, <MCLK_OBUF>, that is driving the following (first 30) non-clock load pins off chip. < PIN: MCLK.O; > This design practice, in Spartan-6, can lead to an unroutable situation due to limitations in the global routing. If the design does route there may be excessive delay or skew on this net. It is recommended to use a Clock Forwarding technique to create a reliable and repeatable low skew solution: instantiate an ODDR2 component; tie the .D0 pin to Logic1; tie the .D1 pin to Logic0; tie the clock net to be forwarded to .C0; tie the inverted clock to .C1. If you wish to override this recommendation, you may use the CLOCK_DEDICATED_ROUTE constraint (given below) in the .ucf file to demote this message to a WARNING and allow your design to continue. Although the net may still not route, you will be able to analyze the failure in FPGA_Editor. < PIN "c1/CLKFX_BUFG_INST.O" CLOCK_DEDICATED_ROUTE = FALSE; > ERRORlace:1136 - This design contains a global buffer instance, <c1/CLKFX_BUFG_INST>, driving the net, <MCLK_OBUF>, that is driving the following (first 30) non-clock load pins. < PIN: MCLK.O; > This is not a recommended design practice in Spartan-6 due to limitations in the global routing that may cause excessive delay, skew or unroutable situations. It is recommended to only use a BUFG resource to drive clock loads. If you wish to override this recommendation, you may use the CLOCK_DEDICATED_ROUTE constraint (given below) in the .ucf file to demote this message to a WARNING and allow your design to continue. < PIN "c1/CLKFX_BUFG_INST.O" CLOCK_DEDICATED_ROUTE = FALSE; > ERRORack:1654 - The timing-driven placement phase encountered an error. Is there something that I can do for the CS4344 project to compile and work ok in my Mimas v1 ? Regards, Christos
Hello Christos, There is no need to make any changes to any file to build CS4344 Audio expansion sample code for Mimas if you are using the batch file available in the zip file. Please see readme.txt for more details on how to build the code using the batch file. I just tried building the code and worked fine (I have Xilinx ISE 14.7). Please see the output log below. Thanks, Tom *************************************************************** Numato Lab *************************************************************** *************************************************************** CS4344 Audio Expansion Module *************************************************************** ** note : If build steps does not execute, please make sure path to Xilinx build tools is registered in PATH variable. Generate bit and bin file for Sr No. Board Supported -------------------------------------------------- 1 Elbert V2 Yes 2 Mimas Yes 3 Mimas V2 Yes 4 Saturn Yes 5 Waxwing Carrier Yes 6 Waxwing Development Board Yes Enter Choice: 2 Sit back and relax while we generate the files for you ERROR:Xst:438 - Can not open file : AudioCS4344ExpansionModule.prj Total REAL time to Xst completion: 0.00 secs Total CPU time to Xst completion: 0.08 secs --> Total memory usage is 160148 kilobytes Number of errors : 1 ( 0 filtered) Number of warnings : 0 ( 0 filtered) Number of infos : 0 ( 0 filtered) Command Line: C:\Xilinx\14.7\ISE_DS\ISE\bin\nt64\unwrapped\ngdbuild.exe -filter iseconfig/filter.filter -intstyle ise -dd _ngo -nt timestamp -uc ucf/MimasExpansion.ucf -p xc6slx9-tqg144-2 build/spartan6/AudioCS4344ExpansionModule.ngc build/spartan6/AudioCS4344ExpansionModule.ngd Reading NGO file "C:/Users/user/Desktop/numatocc-CS4344Audio.r122/CS4344Audio.r122/build/spartan6 /AudioCS4344ExpansionModule.ngc" ... Gathering constraint information from source properties... Done. Annotating constraints to design from ucf file "ucf/MimasExpansion.ucf" ... Resolving constraint associations... Checking Constraint Associations... Done... Checking expanded design ... Partition Implementation Status ------------------------------- No Partitions were found in this design. ------------------------------- NGDBUILD Design Results Summary: Number of errors: 0 Number of warnings: 0 Writing NGD file "build/spartan6/AudioCS4344ExpansionModule.ngd" ... Total REAL time to NGDBUILD completion: 2 sec Total CPU time to NGDBUILD completion: 2 sec Writing NGDBUILD log file "build/spartan6/AudioCS4344ExpansionModule.bld"... NGDBUILD done. Using target part "6slx9tqg144-2". Mapping design into LUTs... Running directed packing... Running delay-based LUT packing... Updating timing models... INFO:Map:215 - The Interim Design Summary has been generated in the MAP Report (.mrp). Running timing-driven placement... Total REAL time at the beginning of Placer: 3 secs Total CPU time at the beginning of Placer: 2 secs Phase 1.1 Initial Placement Analysis Phase 1.1 Initial Placement Analysis (Checksum:60047032) REAL time: 3 secs Phase 2.7 Design Feasibility Check Phase 2.7 Design Feasibility Check (Checksum:60047032) REAL time: 3 secs Phase 3.31 Local Placement Optimization Phase 3.31 Local Placement Optimization (Checksum:60047032) REAL time: 3 secs Phase 4.2 Initial Placement for Architecture Specific Features Phase 4.2 Initial Placement for Architecture Specific Features (Checksum:bbfee472) REAL time: 4 secs Phase 5.36 Local Placement Optimization Phase 5.36 Local Placement Optimization (Checksum:bbfee472) REAL time: 4 secs Phase 6.30 Global Clock Region Assignment Phase 6.30 Global Clock Region Assignment (Checksum:bbfee472) REAL time: 4 secs Phase 7.3 Local Placement Optimization Phase 7.3 Local Placement Optimization (Checksum:bbfee472) REAL time: 4 secs Phase 8.5 Local Placement Optimization Phase 8.5 Local Placement Optimization (Checksum:bbfee472) REAL time: 4 secs Phase 9.8 Global Placement .. .. Phase 9.8 Global Placement (Checksum:a135c0aa) REAL time: 4 secs Phase 10.5 Local Placement Optimization Phase 10.5 Local Placement Optimization (Checksum:a135c0aa) REAL time: 4 secs Phase 11.18 Placement Optimization Phase 11.18 Placement Optimization (Checksum:70e70d2) REAL time: 4 secs Phase 12.5 Local Placement Optimization Phase 12.5 Local Placement Optimization (Checksum:70e70d2) REAL time: 4 secs Phase 13.34 Placement Validation Phase 13.34 Placement Validation (Checksum:70e70d2) REAL time: 4 secs Total REAL time to Placer completion: 4 secs Total CPU time to Placer completion: 4 secs Running post-placement packing... Writing output files... Design Summary: Number of errors: 0 Number of warnings: 0 Slice Logic Utilization: Number of Slice Registers: 44 out of 11,440 1% Number used as Flip Flops: 44 Number used as Latches: 0 Number used as Latch-thrus: 0 Number used as AND/OR logics: 0 Number of Slice LUTs: 57 out of 5,720 1% Number used as logic: 56 out of 5,720 1% Number using O6 output only: 16 Number using O5 output only: 28 Number using O5 and O6: 12 Number used as ROM: 0 Number used as Memory: 0 out of 1,440 0% Number used exclusively as route-thrus: 1 Number with same-slice register load: 0 Number with same-slice carry load: 1 Number with other load: 0 Slice Logic Distribution: Number of occupied Slices: 19 out of 1,430 1% Number of MUXCYs used: 48 out of 2,860 1% Number of LUT Flip Flop pairs used: 57 Number with an unused Flip Flop: 15 out of 57 26% Number with an unused LUT: 0 out of 57 0% Number of fully used LUT-FF pairs: 42 out of 57 73% Number of unique control sets: 2 Number of slice register sites lost to control set restrictions: 12 out of 11,440 1% A LUT Flip Flop pair for this architecture represents one LUT paired with one Flip Flop within a slice. A control set is a unique combination of clock, reset, set, and enable signals for a registered element. The Slice Logic Distribution report is not meaningful if the design is over-mapped for a non-slice resource or if Placement fails. IO Utilization: Number of bonded IOBs: 5 out of 102 4% Number of LOCed IOBs: 5 out of 5 100% Specific Feature Utilization: Number of RAMB16BWERs: 0 out of 32 0% Number of RAMB8BWERs: 0 out of 64 0% Number of BUFIO2/BUFIO2_2CLKs: 0 out of 32 0% Number of BUFIO2FB/BUFIO2FB_2CLKs: 0 out of 32 0% Number of BUFG/BUFGMUXs: 1 out of 16 6% Number used as BUFGs: 1 Number used as BUFGMUX: 0 Number of DCM/DCM_CLKGENs: 0 out of 4 0% Number of ILOGIC2/ISERDES2s: 0 out of 200 0% Number of IODELAY2/IODRP2/IODRP2_MCBs: 0 out of 200 0% Number of OLOGIC2/OSERDES2s: 0 out of 200 0% Number of BSCANs: 0 out of 4 0% Number of BUFHs: 0 out of 128 0% Number of BUFPLLs: 0 out of 8 0% Number of BUFPLL_MCBs: 0 out of 4 0% Number of DSP48A1s: 0 out of 16 0% Number of ICAPs: 0 out of 1 0% Number of MCBs: 0 out of 2 0% Number of PCILOGICSEs: 0 out of 2 0% Number of PLL_ADVs: 0 out of 2 0% Number of PMVs: 0 out of 1 0% Number of STARTUPs: 0 out of 1 0% Number of SUSPEND_SYNCs: 0 out of 1 0% Average Fanout of Non-Clock Nets: 1.81 Peak Memory Usage: 361 MB Total REAL time to MAP completion: 4 secs Total CPU time to MAP completion: 4 secs Mapping completed. See MAP report file "build/spartan6/AudioCS4344ExpansionModule_map.mrp" for details. Constraints file: build/spartan6/AudioCS4344ExpansionModule.pcf. Loading device for application Rf_Device from file '6slx9.nph' in environment C:\Xilinx\14.7\ISE_DS\ISE\. "AudioCS4344ExpansionModule" is an NCD, version 3.2, device xc6slx9, package tqg144, speed -2 Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000 Celsius) Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.260 Volts) Device speed data version: "PRODUCTION 1.23 2013-10-13". Device Utilization Summary: Slice Logic Utilization: Number of Slice Registers: 44 out of 11,440 1% Number used as Flip Flops: 44 Number used as Latches: 0 Number used as Latch-thrus: 0 Number used as AND/OR logics: 0 Number of Slice LUTs: 57 out of 5,720 1% Number used as logic: 56 out of 5,720 1% Number using O6 output only: 16 Number using O5 output only: 28 Number using O5 and O6: 12 Number used as ROM: 0 Number used as Memory: 0 out of 1,440 0% Number used exclusively as route-thrus: 1 Number with same-slice register load: 0 Number with same-slice carry load: 1 Number with other load: 0 Slice Logic Distribution: Number of occupied Slices: 19 out of 1,430 1% Number of MUXCYs used: 48 out of 2,860 1% Number of LUT Flip Flop pairs used: 57 Number with an unused Flip Flop: 15 out of 57 26% Number with an unused LUT: 0 out of 57 0% Number of fully used LUT-FF pairs: 42 out of 57 73% Number of slice register sites lost to control set restrictions: 0 out of 11,440 0% A LUT Flip Flop pair for this architecture represents one LUT paired with one Flip Flop within a slice. A control set is a unique combination of clock, reset, set, and enable signals for a registered element. The Slice Logic Distribution report is not meaningful if the design is over-mapped for a non-slice resource or if Placement fails. IO Utilization: Number of bonded IOBs: 5 out of 102 4% Number of LOCed IOBs: 5 out of 5 100% Specific Feature Utilization: Number of RAMB16BWERs: 0 out of 32 0% Number of RAMB8BWERs: 0 out of 64 0% Number of BUFIO2/BUFIO2_2CLKs: 0 out of 32 0% Number of BUFIO2FB/BUFIO2FB_2CLKs: 0 out of 32 0% Number of BUFG/BUFGMUXs: 1 out of 16 6% Number used as BUFGs: 1 Number used as BUFGMUX: 0 Number of DCM/DCM_CLKGENs: 0 out of 4 0% Number of ILOGIC2/ISERDES2s: 0 out of 200 0% Number of IODELAY2/IODRP2/IODRP2_MCBs: 0 out of 200 0% Number of OLOGIC2/OSERDES2s: 0 out of 200 0% Number of BSCANs: 0 out of 4 0% Number of BUFHs: 0 out of 128 0% Number of BUFPLLs: 0 out of 8 0% Number of BUFPLL_MCBs: 0 out of 4 0% Number of DSP48A1s: 0 out of 16 0% Number of ICAPs: 0 out of 1 0% Number of MCBs: 0 out of 2 0% Number of PCILOGICSEs: 0 out of 2 0% Number of PLL_ADVs: 0 out of 2 0% Number of PMVs: 0 out of 1 0% Number of STARTUPs: 0 out of 1 0% Number of SUSPEND_SYNCs: 0 out of 1 0% Overall effort level (-ol): High Router effort level (-rl): High Starting initial Timing Analysis. REAL time: 3 secs Finished initial Timing Analysis. REAL time: 3 secs Starting Router Phase 1 : 178 unrouted; REAL time: 3 secs Phase 2 : 122 unrouted; REAL time: 3 secs Phase 3 : 25 unrouted; REAL time: 3 secs Phase 4 : 25 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 3 secs Updating file: build/spartan6/AudioCS4344ExpansionModule.ncd with current fully routed design. Phase 5 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 3 secs Phase 6 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 3 secs Phase 7 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 3 secs Phase 8 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 3 secs Phase 9 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 3 secs Phase 10 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 3 secs Total REAL time to Router completion: 3 secs Total CPU time to Router completion: 2 secs Partition Implementation Status ------------------------------- No Partitions were found in this design. ------------------------------- Generating "PAR" statistics. ************************** Generating Clock Report ************************** +---------------------+--------------+------+------+------------+-------------+ | Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)| +---------------------+--------------+------+------+------------+-------------+ | MCLK_OBUF_BUFG | BUFGMUX_X3Y6| No | 15 | 0.027 | 1.447 | +---------------------+--------------+------+------+------------+-------------+ * Net Skew is the difference between the minimum and maximum routing only delays for the net. Note this is different from Clock Skew which is reported in TRCE timing report. Clock Skew is the difference between the minimum and maximum path delays which includes logic delays. * The fanout is the number of component pins not the individual BEL loads, for example SLICE loads not FF loads. Timing Score: 0 (Setup: 0, Hold: 0, Component Switching Limit: 0) Asterisk (*) preceding a constraint indicates it was not met. This may be due to a setup or hold violation. ---------------------------------------------------------------------------------------------------------- Constraint | Check | Worst Case | Best Case | Timing | Timing | | Slack | Achievable | Errors | Score ---------------------------------------------------------------------------------------------------------- NET "MCLK_OBUF" PERIOD = 10 ns HIGH 50% | SETUP | 6.755ns| 3.245ns| 0| 0 | HOLD | 0.437ns| | 0| 0 ---------------------------------------------------------------------------------------------------------- All constraints were met. Generating Pad Report. All signals are completely routed. Total REAL time to PAR completion: 3 secs Total CPU time to PAR completion: 3 secs Peak Memory Usage: 322 MB Placer: Placement generated during map. Routing: Completed - No errors found. Timing: Completed - No errors found. Number of error messages: 0 Number of warning messages: 0 Number of info messages: 0 Writing design to file build/spartan6/AudioCS4344ExpansionModule.ncd PAR done! Loading device for application Rf_Device from file '6slx9.nph' in environment C:\Xilinx\14.7\ISE_DS\ISE\. "AudioCS4344ExpansionModule" is an NCD, version 3.2, device xc6slx9, package tqg144, speed -2 Analysis completed Thu Jun 04 18:41:56 2015 -------------------------------------------------------------------------------- Generating Report ... Number of warnings: 0 Total time: 1 secs build\spartan6\AudioCS4344ExpansionModule_MimasExpansion.bin 1 file(s) copied. build\spartan6\AudioCS4344ExpansionModule_MimasExpansion.bit 1 file(s) copied. *************************************************************** Numato Lab *************************************************************** *************************************************************** CS4344 Audio Expansion Module *************************************************************** Successfull Press Enter to Exit Press any key to continue . . .
Hi Tom, thank you for letting me know this. Its working here too as you indicate. Yet I cannot review the example in the ISE RTL/Technology Viewers this way. Is there a way to have the ISE viewers do inspection even by working with the batch file? Thanks, Christos
The default project file AudioCS4344ExpansionModule.xise works fine as is (this project is configured for Elbert V2 by default). If you make correct changes, it should work just fine with any board. Thanks, Tom
Ok, I know that. I already used the ISE gui with all the other examples and it is working just fine, I have this problem only with the CS4344 example. As I said, when working with ISE gui, the provided CS4344 module example project does give an error as indicated in my first post. On the other hand, if I work with the batch file, it does conclude the compile, but I cannot use the viewers. And I cant seem to find what is the change that the batch file method imposes on the project and passes ok so to put this change myself also in the ISE gui project and work there. I'd be happy if someone point this needed change to me. Christos
Hello Christos, unfortunately I don't have readily usable information/code to help with the situation, sorry about that. All settings/parameters used for building code for Mimas/CS4344 is available within the batch file itself. It shouldn't be very difficult look them up and Thanks, Tom
