I'm currently working on a port of MiSoC to the Mimas V2 and I discovered a very specific failure mode for the built-in UART. Essentially, the UART won't be able to send data from the FPGA to the PC if, after the initial configuration, the SPI/UART switch is in the UART position and the FPGA ties sending data to the PC before the PC has sent any data to the FPGA. I suspect that something in the PIC is stalling somewhere, but I've been having a hard time pinning down the common cause in all of my troubleshooting steps. I've attached two bitstreams (in .bit and .bin form) to this message to aid in debugging: uart_demo.{bit,bin} is a simple echo demo (source code here) misoc_mimasv2.{bit,bin} is my work-in-progress port of MiSoC to the Mimas V2 uart_demo simply waits for a byte to be sent to it, then echoes that byte back to the PC. On the other hand, immediately after misoc_mimasv2 starts up, it will begin sending data out of the serial port. My current workaround it to hold the MiSoC CPU in reset (pressing and holding SW6) when plugging it in until I've sent data to it, but this not ideal. As soon as I can make a list of every test combination I've made, I'll update this thread.
