[Resolved] Elbert V2 interface DHT22

Hi, everyone.
Now i am coding module interface with DHT22 to display LCD. I tested it but

Code:

entity DHT22 is
    generic (
    CLK_PERIOD_NS : positive := 83;    -- 12MHz
    N: positive:= 40);
    port(
        clk,rst : in std_logic ;
--        en    : in std_logic ;
        singer_bus: inout std_logic;
        dataout: out std_logic_vector (N-1 downto 0);
        tick_done: out std_logic
    );
end DHT22;
  
architecture Behavioral of DHT11 is

    constant DELAY_1_MS: positive := 1*10**6/CLK_PERIOD_NS+1;
    constant DELAY_40_US: positive := 40*10**3/CLK_PERIOD_NS+1;
    constant DELAY_80_US: positive := 80*10**3/CLK_PERIOD_NS+1;
    constant DELAY_50_US: positive := 50*10**3/CLK_PERIOD_NS+1;
    constant TIME_70_US: positive := 80*10**3/CLK_PERIOD_NS+1; --bit  > 70 us
    constant TIME_28_uS: positive := 30*10**3/CLK_PERIOD_NS+1; -- bit 0 > 28 us
    constant MAX_DELAY  : positive := 5*10**6/CLK_PERIOD_NS+1; -- 5 ms
  
    type state_type is (reset,start_m,wait_res_sl,response_sl,delay_sl,start_sl,consider_logic,end_sl);
  
    signal  index, next_index : natural range 0 to MAX_DELAY;
    --signal  counter, next_counter: natural range 0 to MAX_DELAY;
    signal  state, next_state : state_type;
    signal     data_out,next_data_out: std_logic_vector (N-1 downto 0);
    signal     bit_in, next_bit_in: std_logic;
    signal  number_bit,next_number_bit: natural range 0 to 40;
    signal     oe: std_logic;

begin  
    --register
    regis_state:process (clk,rst) begin
        if rst = '1' then
            state <= reset;
            index <= MAX_DELAY;
            number_bit <= 0;
            bit_in <= '1';
            data_out <= (others => '0');
        elsif rising_edge(clk) then
            state <= next_state;
            index <= next_index;
            number_bit <= next_number_bit;
            bit_in     <= next_bit_in;
            data_out   <= next_data_out;
        end if;
    end process regis_state;
    proces_state: process (singer_bus,index,state,bit_in,number_bit,data_out) begin
        tick_done <= '0';
        next_data_out <= data_out;
        next_number_bit <= number_bit;
        next_state <= state;
        next_data_out <= data_out;
        next_index <= index;
        dataout <= (others => '0');
        oe <= '0';
        next_bit_in <= bit_in;
        case(state) is
            when reset =>   -- initial
   
                if index = 0 then
                    next_state <= start_m;
                    next_index <= DELAY_1_MS;
                    next_number_bit <= N-1;
                else
                    next_state <= reset;
                    next_index <= index - 1;                  
                end if;
              
            when start_m =>  -- master send '1' in 1ms
                if index = 0 then
                    next_state <= wait_res_sl;
                    next_index <= DELAY_40_US;
                else
                    oe <= '1';
                    next_state <= start_m;
                    next_index <= index -1;
                end if ;
            when wait_res_sl => -- wait for slave response in 40us  -- xem xet th slave tac dong bat cu luc nao
                next_bit_in <= singer_bus;
                if  bit_in ='1' and next_bit_in = '0' then  --
                    next_state <= response_sl;
                else
                    next_state <= wait_res_sl;  
                end if;
            when response_sl => -- slave response in 80us
                next_bit_in <= singer_bus;
                if bit_in ='0' and next_bit_in = '1' then
                    next_state <= delay_sl;
                else
                    next_state <= response_sl;
                end if;
            when delay_sl => -- wait for slave delay in 80us
                if bit_in = '1' and next_bit_in ='0' then
                    next_state <= start_sl;
                else
                    next_state <= delay_sl;
                end if;
            when start_sl => -- start to prepare in 50us               
                if (bit_in = '0') and (next_bit_in = '1') then
                    next_state <= consider_logic;
                    next_index <= 0;
                elsif number_bit = 0 then
                        next_state <= end_sl;
                        next_index <= DELAY_50_US;
                    else
                        next_state <= start_sl;
                end if;
            when consider_logic => -- determine 1 bit-data of slave
                next_index <= index + 1;
                next_bit_in <= singer_bus;
                if bit_in = '1' and next_bit_in = '0' then -- the end of logic state
                    next_number_bit <= number_bit -1;

                    if (index < TIME_28_uS) then
                        next_data_out <= data_out(N-2 downto 0) & '0';
                    elsif (index < TIME_70_US) then
                        next_data_out <= data_out(N-2 downto 0) & '1';
                    end if;
                        next_state <= start_sl;
                        next_index <= DELAY_50_US;  
                elsif bit_in ='1' and next_bit_in ='1' then
                    next_state <= consider_logic;
                end if;
            when end_sl => --
                if index = 0 then
                    next_index <= MAX_DELAY;
                    next_state <= reset;  
                else
                    tick_done <= '1';
                    dataout <= data_out;
                    next_index <= index -1;
                    next_state <= end_sl;  
                end if;
        end case;
    end process proces_state;
    singer_bus <= '0' when oe ='1' else 'Z';
end Behavioral;