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[Resolved] Some Galatea questions + GPIO

Discussion in 'FPGA Boards' started by omstation, Aug 23, 2017.

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  1. omstation

    omstation New Member

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    Sorry to make another thread but ran into some questions that I would like a definitive answer on.

    Just to reiterate, this is the board I am referring about :
    https://numato.com/galatea-pci-express-spartan-6-fpga-development-board/


    Firstly, I noticed this on the product desc :

    "Can be powered from PCIe slot or from an external power supply"


    Just to confirm, I can run this board outside a machine using the 6 pin on the top right of the board?
    I have tested this and a led flashes turns on for about a half a second and then turns off. Which I assume is normal. The 3.3v rails on the io expansion seem to be at the correct voltage so I believe I am correct that it is powered correctly.

    Also, when in a computer, is there any risk if I were to have the 6 pin and pcie plugged in at the same time or can only one be plugged in?



    The next one is my main quesion about gpio and sorts :

    When the gpio module is connected to the P4 expansion slot on the board the P2 Header's 1st pin :

    [​IMG]


    Based off both product sheets, the Spartan 6 connecting pin would be : D18 correct?
    Which seems to be aligned with the example project (galateaPCIeGpio) constraints as such (The constraints file on the product page is far clear on the naming) :
    "NET PORT1[0] LOC = D18 | IOSTANDARD = "LVCMOS33" | DRIVE = 8 | SLEW = FAST; "


    This is my main issue, I cannot seem to get a signal out of the gpio board properly. Using basic verilog code such as this :

    `timescale 1ns / 1ps

    module testModule #(
    parameter FAST_TRAIN = "FALSE"
    ) (
    input CLK1,
    output GPIO_P5
    );


    assign GPIO_P5 = CLK1;

    endmodule


    With constraints as such:
    CONFIG VCCAUX=3.3;
    NET "CLK1" LOC = "G9" | IOSTANDARD = "LVCMOS33" | Period = 100 MHz;
    NET "GPIO_P5" LOC = "H4" | IOSTANDARD = "LVCMOS15" | DRIVE = 8 | SLEW = FAST; # Bank = 3

    I don't get a signal coming out of the gpio expansion board attached to the P4 bus on the galatea and I'm hooked up to the P5 header gpio expansion board using pin 1 for this example which as far as I am aware is H4. I have tested this code on another fpga development board I have and it works fine with both running 100 mhz clocks.



    Some other questions I have are :

    Is there any way to access lets say the D1 led on the board, the one that seems to light up on power on for a split second?
    The only schematic reference I found to the D1 led is this :
    [​IMG]
    So I'm assuming there is no physical connection to the fpga.



    Is there any way to access the "SW1" button on the board.
    Is that this :

    "#NET "RST_N" LOC = "AB19" | IOSTANDARD = "LVCMOS33" | PULLUP ; # Bank = 2"


    What is this header for?
    [​IMG]

    I just went looking in the schematic to see if I could find it and I'm guessing it is this :
    [​IMG]


    Sorry for the long post, just wanted to clear some stuff up.


    Thanks.
     
    Last edited: Aug 23, 2017
  2. rohith

    rohith Moderator Staff Member

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    Hi @omstation ,

    Yes, you can run Galatea externally without any host using via the external power supply connector. The LED which you are mentioning is the configuration LED, which turns off when the FPGA is configured.

    Regarding your design, it would be good to take a look at the (critical) warnings generated by Xilinx. I suspect it might be removing the signal altogether. Can you post complete synthesis and implementation log as attachment here? I strongly suspect that Xilinx is creating incorrect design in this case (ie., connection of clock directly to IO)

    LED D1 cannot be used by users. That LED is connected to DONE pin of FPGA which is active when FPGA is configuring itself. DONE pin is not an IO pin so users cannot control that.

    For SW1, yeah we can use that as an General Purpose Input. Just use the location "AB19" in your constraint and make sure the logic takes into account the active-low signalling of the SW1. Also use pullup in that pin.

    The header which you have mentioned is SPI Header, through which users can program the onboard SPI Flash of Galatea, via any external hardware. Its just provided for convenience if needed.

    Thanks!
     
  3. omstation

    omstation New Member

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    I'm aware that connecting a clock to gpio is not the best idea, just was testing something.

    Here is the full output with the original code.
    https://hastebin.com/raw/bumigigofo


    Here is the full output with this code, something more realistic :

    https://hastebin.com/raw/ineqarohut

    `timescale 1ns / 1ps

    module testModule #(
    parameter FAST_TRAIN = "FALSE"
    ) (
    input RST_N,
    output GPIO_P5
    );


    assign GPIO_P5 = RST_N;

    endmodule

    I am using the example project and deleted most of the files and changed the main module name, thats why it is saying :
    WARNING projectMgmt - File C:/fpga/galateaPCIeGpio/ise/xilinx_pcie_1_1_ep_s6.bit is missing.

    As far as I am aware that should not cause any issues.
     
  4. rohith

    rohith Moderator Staff Member

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    Hi @omstation ,

    This code should work. If possible could you send your complete zipped project so that we can check what seems to be the issue.

    Thanks!
     
  5. omstation

    omstation New Member

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  6. rohith

    rohith Moderator Staff Member

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    Hi @omstation,

    Thanks for the project. We slightly modified that and it's working now (project named `buffer`). There is also a NOT gate project (`notgate`) which you can try. The same 1st Pin of Header P2 of the IO Expansion Module when it is connected to P4 of Galatea is used. Just use a multimeter or LED-with-a-series-resistor on Pin1 of Header P2 of IO Expansion Module connected to P4 of Galatea to test these. Both these projects should work as intended.

    Thanks!
     

    Attached Files:

  7. omstation

    omstation New Member

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    Thanks, testing shortly. could you explain what I was doing wrong or was it an issue with the default project. NotGate code looks the same just flipped because of the switch state..
     
  8. omstation

    omstation New Member

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    Ah! My oscilloscope is showing at-least the not gate project is working beautifully.

    Thanks.
     
  9. omstation

    omstation New Member

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    Is there any tutorial on how to get the program to be in non volatile storage so I don't have to reprogram every restart?
     
  10. rohith

    rohith Moderator Staff Member

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